Computer Architecture Course

Lesson 1 • Sequential Logic and State Machines

Introduces flip-flops, registers, and finite state machines that store and sequence information. Bridges combinational logic to the concept of processor state.

Lesson 2 • Von Neumann and Harvard Architectures

Compares the two dominant architectural models governing how instructions and data are stored and fetched. Sets the stage for instruction set and memory discussions.

Lesson 3 • History and Evolution of Computing

Traces computing from mechanical calculators to modern processors, establishing why architectural decisions were made. Provides historical context for every concept introduced later.

Lesson 4 • Number Systems and Data Representation

Explains binary, octal, hexadecimal, and signed number formats used inside processors. Grounds students in how all data is physically encoded.

Lesson 1 • Instruction Types and Operations

Categorizes arithmetic, logical, data transfer, control flow, and special instructions. Shows how operation coverage affects compiler and programmer capability.

Lesson 2 • ISA Roles and Classification

Defines what an ISA specifies and how RISC vs. CISC philosophies differ in design goals. Establishes vocabulary used throughout processor design chapters.

Lesson 3 • Assembly Language Programming Basics

Translates ISA concepts into hands-on assembly coding, reinforcing instruction format and addressing mode knowledge. Provides practical grounding before microarchitecture study.

Lesson 4 • Instruction Formats and Encoding

Covers fixed-length, variable-length, and hybrid instruction formats and their impact on decode complexity. Connects encoding choices to pipeline efficiency.

Lesson 1 • Register File and Data Memory

Explains register file organization, read/write ports, and data memory interfacing within the datapath. Connects storage elements to instruction execution flow.

Lesson 2 • Performance Analysis of Single-Cycle Design

Measures clock period, CPI, and throughput of the single-cycle processor, exposing its inefficiency. Motivates the pipelining techniques introduced in the next chapter.

Lesson 3 • Control Unit Design

Derives control signals from opcode fields using truth tables and logic minimization. Shows how the control unit orchestrates every datapath component per instruction.

Lesson 4 • ALU Design and Operation

Constructs arithmetic logic units supporting addition, subtraction, and bitwise operations with carry and overflow detection. Anchors datapath design in concrete hardware.

Lesson 1 • Structural Hazards and Resource Conflicts

Examines resource conflicts from shared memory and functional units and resolves them through duplication or scheduling. Completes the hazard taxonomy for pipeline design.

Lesson 2 • Data Hazards and Forwarding

Identifies RAW, WAR, and WAW hazards and resolves them through forwarding paths and stall insertion. Demonstrates how forwarding eliminates most data hazard penalties.

Lesson 3 • Advanced Pipeline Techniques

Extends basic pipelining to deeper pipelines, superpipelining, and exception handling within a pipeline. Prepares students for superscalar and out-of-order execution concepts.

Lesson 4 • Pipeline Fundamentals

Introduces the five-stage pipeline model and explains how instruction overlap increases throughput. Establishes stage boundaries and inter-stage registers.

Lesson 1 • Main Memory and Storage Technologies

Describes DRAM organization, SDRAM variants, and storage device characteristics including SSDs. Completes the hierarchy picture from cache to persistent storage.

Lesson 2 • Cache Performance Optimization

Applies prefetching, victim caches, critical-word-first, and compiler optimizations to reduce miss penalties. Quantifies improvement using AMAT analysis.

Lesson 3 • Cache Organization and Mapping

Covers direct-mapped, set-associative, and fully associative cache organizations and their hit rate implications. Connects mapping policy to hardware complexity and performance.

Lesson 4 • Memory Hierarchy Principles

Explains locality of reference, hierarchy levels, and the cost-capacity-speed trade-off driving hierarchy design. Frames all subsequent cache and memory discussions.

Lesson 1 • VLIW and Compiler-Scheduled Parallelism

Contrasts hardware-centric OOO with compiler-driven VLIW approaches to ILP exploitation. Evaluates code density, binary compatibility, and scheduling complexity.

Lesson 2 • Tomasulo's Algorithm and Reservation Stations

Explains register renaming via reservation stations and how Tomasulo's algorithm enables out-of-order execution. Resolves WAR and WAW hazards dynamically.

Lesson 3 • Reorder Buffer and Precise Exceptions

Introduces the reorder buffer to commit results in order while executing out of order. Ensures precise exception semantics in OOO processors.

Lesson 4 • Instruction-Level Parallelism Concepts

Defines ILP, true and false dependencies, and the theoretical limits on parallel instruction execution. Establishes the motivation for superscalar and OOO designs.

Lesson 1 • Interconnection Networks

Evaluates bus, crossbar, mesh, torus, and fat-tree topologies for latency, bandwidth, and cost. Connects network design to multiprocessor scalability limits.

Lesson 2 • GPU and Data-Parallel Architectures

Examines GPU streaming multiprocessor design, warp execution, and memory hierarchy for data-parallel workloads. Contrasts GPU throughput optimization with CPU latency optimization.

Lesson 3 • Cache Coherence Protocols

Explains the coherence problem in shared-memory systems and implements snooping and directory protocols. Connects protocol choice to scalability and traffic overhead.

Lesson 4 • Parallel Computing Taxonomy

Classifies parallel architectures using Flynn's taxonomy and distinguishes SIMD, MIMD, and hybrid models. Provides a framework for evaluating all parallel system designs.

Lesson 1 • System-on-Chip Integration

Examines SoC design integrating CPU, GPU, memory controllers, and I/O on a single die. Evaluates on-chip interconnect, power domains, and design trade-offs.

Lesson 2 • Programmed, Interrupt-Driven, and DMA I/O

Compares polling, interrupt-driven, and DMA transfer modes for CPU utilization and throughput. Shows when each mode is appropriate for different device speeds.

Lesson 3 • I/O System Fundamentals

Defines I/O device characteristics, transfer rates, and the role of controllers in abstracting hardware. Establishes the I/O performance metrics used throughout the chapter.

Lesson 4 • Bus Architecture and Protocols

Analyzes synchronous and asynchronous bus designs, arbitration schemes, and bandwidth limitations. Connects bus design to system-level performance constraints.