Digital Electronics Course

Lesson 1 • Boolean Algebra Fundamentals

Introduces Boolean variables, axioms, and theorems for logic simplification. Provides the mathematical framework for designing and reducing logic circuits.

Lesson 2 • Logic Gates and Truth Tables

Examines standard gate types, their symbols, and truth table construction. Links abstract Boolean expressions to physical gate implementations.

Lesson 3 • Number Systems and Conversions

Covers binary, octal, and hexadecimal systems and inter-base conversion methods. Establishes the numerical language used throughout all digital circuit analysis.

Lesson 4 • Karnaugh Map Simplification

Teaches K-map grouping rules for minimising Sum-of-Products and Product-of-Sums expressions. Reduces gate count and circuit complexity systematically.

Lesson 1 • Encoders and Decoders

Explains priority encoders, binary decoders, and seven-segment display drivers. Connects encoding logic to real display and address-decoding applications.

Lesson 2 • Multiplexers and Demultiplexers

Covers MUX/DEMUX operation, select-line control, and function implementation using multiplexers. Demonstrates data routing as a universal logic tool.

Lesson 3 • Combinational Circuit Timing Analysis

Analyses propagation delay, glitches, and critical path timing in combinational networks. Prepares students to meet timing constraints in real designs.

Lesson 4 • Comparators and Code Converters

Designs magnitude comparators and code-conversion circuits for BCD and Gray code. Reinforces Boolean design methodology with practical data-processing circuits.

Lesson 1 • Registers and Shift Registers

Designs parallel-load registers and serial/parallel shift registers for data storage and movement. Connects flip-flop arrays to practical data-handling circuits.

Lesson 2 • Edge-Triggered Flip-Flops

Covers D, JK, T, and SR flip-flops with edge-triggering and preset/clear inputs. Provides the core storage primitives for all sequential circuit design.

Lesson 3 • Latches and Basic Memory Elements

Introduces SR, D, and gated latches as fundamental bistable circuits. Establishes how feedback creates stable state storage in digital systems.

Lesson 4 • Clock Distribution and Timing Constraints

Examines clock skew, jitter, and synchronous design rules for reliable sequential circuits. Ensures students apply timing discipline to all clocked designs.

Lesson 1 • FSM Verification and Simulation

Verifies FSM correctness through timing diagrams, simulation waveforms, and state coverage analysis. Builds confidence in design correctness before implementation.

Lesson 2 • FSM Concepts and State Diagrams

Defines states, transitions, inputs, and outputs for Mealy and Moore models. Establishes the formal framework for all sequential behaviour specification.

Lesson 3 • Next-State and Output Logic Derivation

Derives next-state and output Boolean equations from state tables using K-maps. Produces the combinational logic that drives flip-flop inputs and outputs.

Lesson 4 • State Encoding and Flip-Flop Selection

Applies binary, Gray, and one-hot encoding strategies and selects appropriate flip-flop types. Links encoding choice to circuit complexity and timing performance.

Lesson 1 • ALU Function Unit Design

Integrates adder, logic, and shift units with function-select multiplexers into a complete ALU. Demonstrates how arithmetic and logic operations share hardware resources.

Lesson 2 • Floating-Point Representation and Operations

Explains IEEE 754 single and double precision formats, rounding modes, and basic FP addition. Introduces floating-point hardware as an extension of integer arithmetic units.

Lesson 3 • Binary Multiplication Techniques

Implements shift-and-add, Booth encoding, and array multiplier architectures for binary multiplication. Extends arithmetic design skills to multi-cycle and pipelined operations.

Lesson 4 • Fast Adder Architectures

Compares carry lookahead, carry-select, and prefix adder topologies for speed optimisation. Builds on ripple-carry adders to achieve high-performance arithmetic units.

Lesson 1 • Memory Expansion and Interfacing

Designs word-width and address-space expansion using multiple memory chips. Covers chip-select decoding and bus timing for reliable memory interfacing.

Lesson 2 • Flash Memory Architecture

Examines NOR and NAND flash cell arrays, erase blocks, and wear-levelling principles. Connects flash technology to embedded storage and solid-state drive design.

Lesson 3 • ROM Types and Programming

Covers mask ROM, PROM, EPROM, and EEPROM structures and programming methods. Establishes non-volatile storage options for embedded and look-up table applications.

Lesson 4 • Static and Dynamic RAM

Compares SRAM six-transistor cells with DRAM capacitor cells for speed and density. Explains refresh cycles, access timing, and read/write control signals.

Lesson 1 • HDL-Based Design Entry

Introduces VHDL and Verilog syntax for describing combinational and sequential logic. Connects hardware description languages to programmable device implementation.

Lesson 2 • Synthesis, Place, and Route

Walks through synthesis, technology mapping, placement, and routing steps in FPGA design flow. Prepares students to generate and verify bitstream files for device programming.

Lesson 3 • CPLD Architecture and Configuration

Covers CPLD logic blocks, interconnect matrices, and non-volatile configuration storage. Extends PAL concepts to larger, more complex programmable devices.

Lesson 4 • PAL and PLA Architecture

Explains programmable AND-OR arrays, fuse maps, and output macrocells in PAL/PLA devices. Provides the foundation for understanding all programmable logic structures.

Lesson 1 • Bus Architectures and Interconnects

Covers shared bus, point-to-point, and crossbar interconnect topologies for subsystem communication. Connects memory, processor, and peripheral blocks into a coherent system.

Lesson 2 • Functional and Structural Verification

Applies simulation, formal verification, and equivalence checking to validate design correctness. Ensures the implemented circuit matches the behavioural specification.

Lesson 3 • Register-Transfer Level Design

Describes systems as datapath and control unit pairs using RTL notation and state machines. Provides the abstraction layer between logic gates and system-level architecture.

Lesson 4 • Prototyping and Bring-Up Procedures

Guides FPGA prototype bring-up, logic analyser probing, and iterative debug cycles. Prepares students to transition verified designs from simulation to physical hardware.