Verilog Course

Lesson 1 • Verilog Design Flow and Toolchain

This walks through the end-to-end FPGA and ASIC design flow using Verilog. Students understand where each tool fits before writing any code.

Lesson 2 • Digital Logic Fundamentals Review

This covers binary arithmetic, Boolean algebra, and logic gates as prerequisites. It anchors Verilog syntax in real hardware behaviour that students will model.

Lesson 3 • Hardware Description Languages Overview

This distinguishes HDLs from software programming languages and surveys the HDL landscape. It positions Verilog as a simulation and synthesis tool.

Lesson 1 • Compiler Directives and System Tasks

This introduces `define, `include, `timescale, and common system tasks. Students control simulation behaviour and organise multi-file projects.

Lesson 2 • Operators and Expressions

This covers arithmetic, relational, logical, bitwise, and reduction operators. Students evaluate operator precedence to write unambiguous expressions.

Lesson 3 • Module Structure and Port Declarations

This defines the module as Verilog's fundamental design unit and explains port directions. Students write complete, compilable module skeletons.

Lesson 4 • Nets, Registers, and Variable Types

This differentiates wire, reg, and logic types and explains their hardware implications. Correct type selection prevents common simulation mismatches.

Lesson 1 • Always Blocks for Combinational Logic

This explains how always @(*) models combinational behaviour procedurally. Students avoid latches by correctly specifying sensitivity lists.

Lesson 2 • Modeling Common Combinational Circuits

This applies learned constructs to build encoders, decoders, multiplexers, and adders. It reinforces design patterns used repeatedly in larger systems.

Lesson 3 • Continuous Assignments

This introduces the assign statement for dataflow-level combinational modelling. Students express Boolean functions concisely without procedural blocks.

Lesson 1 • Flip-Flop and Latch Modeling

This models D, T, JK, and SR flip-flops and level-sensitive latches. Students distinguish when each element is appropriate and synthesizable.

Lesson 2 • Registers and Shift Registers

This extends single flip-flops to multi-bit registers and serial shift registers. Students build SIPO, PISO, and PIPO configurations.

Lesson 3 • Clocked Always Blocks and Edge Sensitivity

This introduces posedge and negedge triggers for synchronous design. Students write flip-flop templates that synthesize to real registers.

Lesson 4 • Counters and Frequency Dividers

This designs synchronous and asynchronous counters with modulus control. Students implement up, down, and up-down counters with terminal count.

Lesson 1 • Two-Always-Block FSM Template

This presents the industry-standard two-always-block coding style for FSMs. Students separate state register and next-state logic for clarity and synthesis.

Lesson 2 • Practical FSM Case Studies

This implements traffic light controller, serial receiver, and vending machine FSMs. Students apply the full design-to-verification cycle on realistic problems.

Lesson 3 • FSM Theory and State Diagrams

This reviews Moore and Mealy models, state diagrams, and state tables. It provides the theoretical foundation before any Verilog coding begins.

Lesson 4 • Safe State Encoding and Recovery

This addresses illegal state entry, one-hot encoding hazards, and safe defaults. Students add defensive coding to prevent FSM lockup in hardware.

Lesson 1 • Reusable Component Libraries

This organises modules into libraries using include files and package-like structures. Students adopt naming conventions and file organisation for team projects.

Lesson 2 • Designing a Parameterized ALU

This integrates adder, subtractor, logic unit, and shifter into a configurable ALU. Students practise top-down decomposition and bottom-up integration.

Lesson 3 • Module Instantiation and Hierarchy

This explains named and positional port connections and multi-level hierarchy. Students build a top-level design from pre-designed sub-modules.

Lesson 1 • Response Checking and Assertions

This automates output verification using if-based checkers and immediate assertions. Students eliminate manual waveform inspection for regression testing.

Lesson 2 • Testbench Architecture and Structure

This defines testbench components: DUT instantiation, clock generation, and stimulus. Students write a complete testbench skeleton for any combinational module.

Lesson 3 • Stimulus Generation Techniques

This covers directed, random, and file-driven stimulus methods. Students select the appropriate technique based on design complexity and coverage goals.

Lesson 4 • Waveform Analysis and Debugging

This uses VCD dump and waveform viewers to diagnose simulation failures. Students correlate waveform anomalies with RTL code defects.

Lesson 1 • RTL Coding Guidelines for Synthesis

This presents industry coding rules for registers, combinational logic, and FSMs. Consistent style reduces synthesis warnings and improves tool predictability.

Lesson 2 • Clock Domain Crossing Techniques

This explains metastability risks and synchronisation strategies for multi-clock designs. Students implement two-flop synchronisers and handshake protocols.

Lesson 3 • Timing Constraints and Critical Path Analysis

This reads synthesis timing reports to identify critical paths and slack violations. Students apply RTL changes to meet setup and hold time requirements.

Lesson 4 • Synthesizable vs. Non-Synthesizable Constructs

This identifies constructs legal in simulation but unsupported by synthesis tools. Students audit existing code and replace non-synthesizable patterns.