Electronic Design Course

Lesson 1 • Thevenin and Norton Equivalents

Complex networks are reduced to simple two-terminal models for load analysis. These equivalents simplify iterative design and troubleshooting tasks.

Lesson 2 • Electrical Quantities and Units

Voltage, current, resistance, and power are defined with SI units. These quantities form the measurement language used throughout all circuit analysis.

Lesson 3 • Circuit Laws and Analysis Techniques

Kirchhoff's voltage and current laws are applied to solve multi-loop circuits. Nodal and mesh analysis methods extend these laws to complex networks.

Lesson 4 • Passive Component Fundamentals

Resistors, capacitors, and inductors are characterized by their electrical behavior. Understanding each component's V-I relationship enables accurate circuit modeling.

Lesson 1 • Field-Effect Transistor Fundamentals

MOSFET and JFET operation, threshold voltage, and transconductance are covered. FET biasing and small-signal models prepare students for amplifier stages.

Lesson 2 • Bipolar Junction Transistor Operation

BJT regions of operation and current gain are examined using the Ebers-Moll model. DC biasing establishes the operating point for amplifier design.

Lesson 3 • Diode Characteristics and Applications

The diode V-I curve, forward voltage, and reverse breakdown are analyzed. Rectifier, clipping, and clamping circuits demonstrate practical diode use.

Lesson 4 • Special-Purpose Semiconductor Devices

Zener diodes, Schottky diodes, and thyristors are characterized for regulation and switching. Device selection criteria are linked to application requirements.

Lesson 1 • Common-Emitter and Common-Source Stages

The inverting amplifier topology is analyzed for voltage gain and frequency response. Bypass and coupling capacitors are sized to meet bandwidth requirements.

Lesson 2 • Amplifier Frequency Response and Stability

Bode plots characterize gain and phase across frequency, identifying dominant poles. Stability margins are evaluated to prevent oscillation in feedback amplifiers.

Lesson 3 • Small-Signal Amplifier Models

Hybrid-pi and T-models translate transistor physics into linear circuit equivalents. These models enable AC gain and impedance calculations for amplifier stages.

Lesson 4 • Multi-Stage Amplifier Design

Cascaded stages are analyzed for overall gain, bandwidth shrinkage, and interstage loading. Design strategies maintain signal integrity across multiple stages.

Lesson 1 • Ideal Op-Amp Analysis

Virtual short and infinite input impedance assumptions simplify inverting and non-inverting circuit analysis. Gain equations are derived for fundamental configurations.

Lesson 2 • Non-Ideal Op-Amp Parameters

Offset voltage, bias current, slew rate, and CMRR limit real circuit performance. Compensation techniques minimize errors in precision applications.

Lesson 3 • Active Filter Design

Sallen-Key and multiple-feedback topologies implement low-pass, high-pass, and band-pass responses. Filter order and Q factor are selected to meet attenuation specs.

Lesson 4 • Instrumentation and Precision Amplifiers

Three-op-amp instrumentation amplifiers achieve high CMRR for sensor signal conditioning. Precision rectifiers and peak detectors extend op-amp utility.

Lesson 1 • Number Systems and Boolean Algebra

Binary, hexadecimal, and BCD representations underpin digital system design. Boolean theorems and De Morgan's laws enable algebraic simplification of logic expressions.

Lesson 2 • Logic Gate Families and Electrical Characteristics

CMOS and TTL gate families are compared for speed, power, and noise immunity. Fan-out, propagation delay, and logic levels guide technology selection.

Lesson 3 • Combinational Building Blocks

Encoders, decoders, multiplexers, and demultiplexers are designed and applied as modular building blocks. Adders and comparators extend combinational design to arithmetic functions.

Lesson 4 • Hazards and Timing in Combinational Logic

Static and dynamic hazards cause glitches that corrupt digital outputs. Hazard detection and elimination techniques ensure reliable combinational circuit operation.

Lesson 1 • Finite State Machine Design

Mealy and Moore FSMs are specified with state diagrams and implemented with flip-flops and combinational logic. State encoding strategies affect area and speed.

Lesson 2 • Synchronous System Timing Analysis

Clock-to-Q delay, combinational path delay, and setup time determine maximum operating frequency. Timing closure methods resolve critical path violations.

Lesson 3 • Latches and Flip-Flops

SR, D, JK, and T flip-flops store binary state and respond to clock edges. Setup, hold, and propagation times define reliable clocking constraints.

Lesson 4 • Synchronous Counter Design

Binary, BCD, and modulo-N counters are designed using flip-flop excitation tables. State diagrams guide the derivation of next-state and output logic.

Lesson 1 • Rectifier and Filter Design

Half-wave, full-wave, and bridge rectifiers convert AC to pulsating DC. Capacitive and LC filters reduce ripple to acceptable levels for downstream circuits.

Lesson 2 • Linear Voltage Regulators

Series-pass and shunt linear regulators maintain stable output voltage under load variation. Dropout voltage, power dissipation, and thermal management are analyzed.

Lesson 3 • Feedback Control in Power Supplies

Voltage-mode and current-mode control loops regulate output against load and line disturbances. Compensation network design ensures stability and transient response.

Lesson 4 • Switching Regulator Fundamentals

Buck, boost, and buck-boost topologies convert voltage levels with high efficiency. Duty cycle, inductor sizing, and output capacitor selection are derived analytically.

Lesson 1 • PCB Stack-Up and Layer Planning

Layer count, dielectric material, and copper weight are selected to meet impedance and thermal targets. Power and ground plane placement reduces noise and EMI.

Lesson 2 • Design for Manufacture and Test

Gerber files, bill of materials, and assembly drawings communicate design intent to manufacturers. Test point placement and boundary scan support production testing.

Lesson 3 • Schematic Capture and Netlist Generation

Hierarchical schematics organize complex designs into manageable blocks with clear interfaces. Netlist export links schematic data to layout and simulation tools.

Lesson 4 • Component Placement and Routing

Placement follows signal flow and thermal constraints to minimize trace length and crosstalk. Routing rules enforce clearance, via usage, and differential pair matching.