PCIE Training

Lesson 1 • History and Evolution of PCIe

Traces PCIe from legacy parallel buses to serial point-to-point links. Provides context for why PCIe replaced older interconnects in modern systems.

Lesson 2 • Lane, Link, and Port Concepts

Defines lanes, links, and ports as the physical building blocks of PCIe. Clarifies how width and speed combine to determine bandwidth.

Lesson 3 • PCIe Specification Versions

Compares PCIe Gen 1 through Gen 6 specifications and their data rates. Enables selection of the correct spec version for a given design target.

Lesson 1 • Flow Control Mechanisms

Explains credit-based flow control for posted, non-posted, and completion buffers. Demonstrates how credits prevent receiver overflow.

Lesson 2 • Data Link Layer Operations

Explains DLLP types, ACK/NAK protocol, and flow control initialization. Shows how the data link layer ensures reliable TLP delivery.

Lesson 3 • Transaction Layer Fundamentals

Covers TLP types, address spaces, and ordering rules at the transaction layer. Anchors understanding of how software requests become packets.

Lesson 4 • TLP Routing and Addressing

Covers ID-based, address-based, and implicit routing for TLPs. Ties routing rules to switch forwarding and endpoint response behavior.

Lesson 1 • Equalization and Signal Integrity

Covers transmitter and receiver equalization procedures introduced in Gen 3 and later. Links equalization to reliable high-speed operation.

Lesson 2 • Link Recovery and Error Handling

Examines conditions that trigger recovery and the steps to restore link operation. Prepares students to diagnose intermittent link failures.

Lesson 3 • Configuration and Lane Negotiation

Explains lane reversal, polarity inversion, and link width negotiation. Shows how mismatched widths are resolved during configuration.

Lesson 4 • Receiver Detection and Polling

Details how a transmitter detects a receiver and negotiates bit rate. Connects electrical detection to the start of link training.

Lesson 1 • PCIe Capability Structures

Covers the linked-list capability structure and key standard capabilities. Enables navigation of capability chains during device enumeration.

Lesson 2 • Device Enumeration Process

Walks through bus enumeration, resource allocation, and bridge programming. Ties configuration space knowledge to system boot-time initialization.

Lesson 3 • Configuration Space Layout

Maps the Type 0 and Type 1 configuration header fields and their meanings. Establishes the register map used throughout device bring-up.

Lesson 4 • Base Address Registers

Explains BAR sizing, memory vs. I/O BARs, and 64-bit BAR pairs. Connects BAR programming to system address map allocation.

Lesson 1 • PCIe Power State Overview

Introduces D-states, L-states, and their relationships to system power states. Provides the vocabulary for all subsequent power management topics.

Lesson 2 • Device Power State Transitions

Explains D-state transitions, PME generation, and software-initiated wake. Links device power states to driver and firmware responsibilities.

Lesson 3 • L1 Substates and CLKREQ

Details L1.1 and L1.2 substates and the CLKREQ signal protocol. Shows how clock gating in L1 substates achieves deeper power savings.

Lesson 1 • Advanced Error Reporting

Covers AER capability registers, error logging, and interrupt generation. Enables precise error diagnosis using hardware-reported information.

Lesson 2 • Data Integrity and ECC Techniques

Covers LCRC, ECRC, and end-to-end data integrity protection mechanisms. Ties integrity features to system reliability and safety requirements.

Lesson 3 • PCIe Error Classification

Distinguishes correctable, uncorrectable non-fatal, and uncorrectable fatal errors. Establishes the severity framework used in all error handling decisions.

Lesson 4 • Error Forwarding and Signaling

Explains ERR_COR, ERR_NONFATAL, and ERR_FATAL message propagation. Connects error signaling to system-level error management software.

Lesson 1 • TLP Payload and MPS Tuning

Explains max payload size, max read request size, and their effect on efficiency. Connects MPS and MRRS settings to measurable throughput gains.

Lesson 2 • Credit and Queue Depth Optimization

Analyzes flow control credit allocation and its effect on pipeline utilization. Shows how credit starvation degrades throughput and how to prevent it.

Lesson 3 • DMA and Scatter-Gather Efficiency

Covers DMA engine design, scatter-gather list optimization, and descriptor management. Links DMA efficiency to CPU offload and system throughput.

Lesson 4 • Bandwidth and Latency Fundamentals

Quantifies theoretical vs. effective bandwidth and sources of latency overhead. Provides the measurement baseline for all optimization work.

Lesson 1 • Peer-to-Peer DMA Transfers

Explains peer-to-peer DMA routing, ACS policy, and fabric topology requirements. Enables direct device-to-device transfers without CPU involvement.

Lesson 2 • CEM and Form Factor Requirements

Covers card electromechanical spec requirements for add-in cards and slots. Ensures physical and electrical compatibility across PCIe form factors.

Lesson 3 • PCIe Compliance Testing Process

Outlines the compliance test suite, test fixtures, and pass/fail criteria. Prepares students to execute and interpret official compliance test results.

Lesson 4 • SR-IOV and Virtualization Support

Covers SR-IOV capability, VF enumeration, and hypervisor integration. Connects virtualization features to cloud and data center deployment scenarios.