Computer Organization Course

Lesson 1 • Boolean Algebra and Logic Gates

Presents Boolean laws, theorems, and their physical realization as logic gates. This mathematical foundation is essential for designing all digital circuits covered later.

Lesson 2 • Basic Computer System Structure

Introduces the major functional units: CPU, memory, I/O, and interconnects. Establishes the von Neumann model as the reference architecture for the course.

Lesson 3 • History and Evolution of Computers

Traces computing from mechanical calculators to modern processors. Provides historical context that motivates architectural design decisions studied throughout the course.

Lesson 4 • Performance Metrics and Benchmarking

Defines clock speed, CPI, MIPS, and FLOPS as quantitative measures of performance. Students learn to evaluate and compare computer systems objectively.

Lesson 1 • Comparators and Shifters

Constructs magnitude comparators and barrel shifters at the gate level. These circuits support comparison and shift operations required by instruction execution.

Lesson 2 • Combinational Building Blocks

Covers multiplexers, demultiplexers, encoders, and decoders as standard combinational modules. These blocks appear directly in ALU and control path designs.

Lesson 3 • Arithmetic Circuits

Designs half adders, full adders, ripple-carry, and carry-lookahead adders. Arithmetic circuits form the computational core of every ALU studied in later chapters.

Lesson 4 • Karnaugh Maps and Minimization

Applies K-map grouping to minimize Boolean expressions systematically. Minimized expressions reduce gate count and propagation delay in hardware designs.

Lesson 1 • Counters and Timing Circuits

Designs synchronous and asynchronous counters and ring oscillators. Counters drive program counters, timers, and address sequencers in processor designs.

Lesson 2 • Synchronous Design and Clock Distribution

Addresses clock skew, metastability, and synchronizer design in clocked systems. Reliable synchronous design is mandatory before studying pipelined processor timing.

Lesson 3 • Registers and Shift Registers

Builds parallel-load registers and serial shift registers from flip-flops. Registers are the primary data-holding elements inside every CPU datapath.

Lesson 4 • Finite-State Machine Design

Formalizes Mealy and Moore FSM models and the state-diagram-to-circuit flow. FSMs implement control units that sequence operations in processor pipelines.

Lesson 1 • Instruction Types and Operations

Catalogs data transfer, arithmetic, logical, shift, and control-flow instructions. A complete instruction taxonomy is required to design a functional ALU and control unit.

Lesson 2 • Addressing Modes

Explains immediate, register, direct, indirect, indexed, and relative addressing. Addressing modes determine how operands are located and affect memory access patterns.

Lesson 3 • ISA Design Principles

Covers instruction format, operand types, and design trade-offs between simplicity and expressiveness. ISA choices directly determine datapath complexity and compiler efficiency.

Lesson 4 • Assembly Language Programming

Translates high-level constructs into assembly using a representative ISA. Hands-on assembly coding solidifies understanding of instruction encoding and execution flow.

Lesson 1 • ALU Design and Operation

Builds a multi-function ALU supporting arithmetic, logical, and shift operations with status flags. The ALU is the computational heart of every datapath designed in this chapter.

Lesson 2 • Microprogrammed Control Units

Implements control logic as a microprogram stored in a control ROM. Microprogramming enables flexible instruction set extension and simplifies complex control sequences.

Lesson 3 • Multi-Cycle Processor Design

Partitions instruction execution into multiple shorter cycles to improve clock frequency. Multi-cycle design introduces state-machine control and resource sharing concepts.

Lesson 4 • Register File and Data Paths

Designs a multi-port register file and traces data flow through fetch, decode, execute, and write-back. Data path wiring determines instruction latency and resource conflicts.

Lesson 1 • Structural Hazards and Resource Conflicts

Examines memory and functional-unit conflicts that arise from shared pipeline resources. Structural hazard analysis guides decisions about resource duplication and scheduling.

Lesson 2 • Pipeline Fundamentals

Introduces the pipeline stages, inter-stage registers, and ideal throughput model. Understanding the ideal case establishes the baseline from which hazard costs are measured.

Lesson 3 • Advanced Pipeline Techniques

Surveys superscalar issue, out-of-order execution, and speculative execution concepts. These techniques extend single-pipeline ILP and motivate the advanced architecture topics ahead.

Lesson 4 • Data Hazards and Forwarding

Identifies RAW, WAR, and WAW hazards and resolves them via forwarding paths and stalls. Hazard resolution is critical for maintaining correct execution in all pipelined processors.

Lesson 1 • Cache Performance Analysis

Applies the AMAT formula to quantify miss penalty, miss rate, and hit time contributions. Quantitative analysis guides architectural decisions for multi-level cache hierarchies.

Lesson 2 • Replacement and Write Policies

Evaluates LRU, FIFO, and random replacement and write-through vs. write-back policies. Policy selection significantly affects miss rate, bandwidth, and coherence complexity.

Lesson 3 • Cache Organization and Mapping

Covers direct-mapped, set-associative, and fully associative cache structures. Mapping policy determines hit rate and hardware complexity for a given workload.

Lesson 4 • Memory Technology Overview

Compares SRAM, DRAM, flash, and magnetic storage on speed, density, and cost. Technology trade-offs explain why a hierarchy is necessary and how each level is used.

Lesson 1 • Direct Memory Access

Designs DMA controllers that transfer data between memory and devices without CPU involvement. DMA dramatically increases I/O bandwidth for block-transfer peripherals.

Lesson 2 • I/O Interface Fundamentals

Covers memory-mapped vs. port-mapped I/O, device registers, and polling. These fundamentals establish how software communicates with hardware peripherals.

Lesson 3 • Bus Architecture and Protocols

Analyzes synchronous and asynchronous bus protocols, arbitration, and bandwidth limits. Bus design determines the maximum data rate between all system components.

Lesson 4 • Modern Interconnect Standards

Surveys point-to-point serial interconnects, PCIe topology, and network-on-chip concepts. Modern interconnects replace shared buses to meet bandwidth demands of multi-core systems.